The present invention relates to a memory device, whereby a command, row address, bank address and column address are provided in a packet format from a memory controller, and more particularly to a clock-synchronized memory device, which comprises a scheduler, which makes it possible to control latency from the supply of a command to the start of an internal circuit operation, such as the start of a column side operation.
With Synchronous Dynamic Random Access Memory (SDRAM), which has come into widespread use recently as highspeed memory, a command and address or data are supplied in synch with an external clock, and after a prescribed interval, read data is output in synch with an external clock. For such SDRAM, a command input pin, which inputs a command signal, and an address input pin, which inputs a row address or column address, are provided separately. And then, a command signal and an address signal required for that command are provided simultaneously.
Principal commands include an Active command, which drives a word line corresponding to a row address, a Read command, which reads data from a column corresponding to a column address, a Write command, which writes data to a column corresponding to a column address, a Precharge command, which closes a word line and precharges a bit line, and a Refresh command, which performs refresh. A memory controller, which controls a memory device, performs various controls by supplying these commands to the memory device together with an address and data subordinate thereto.
For example, when reading data from memory, first an Active command is supplied together with a row address, then, after a prescribed interval (latency), a Read command is supplied together with a column address, and finally, a Precharge command is supplied. Further, in the burst mode, whereby a plurality of bits are read out consecutively, after an Active command is supplied together with a row address, read commands are supplied sequentially at a prescribed timing with a continuously changing column address. Further, when writing data to memory, an active command is supplied together with a row address, and after a prescribed interval (latency), a write command is supplied together with a column address and write data.
However, the above-described commands are divided into a command that requests a row side operation, and a command that requests a column side operation, and, in accordance with the operating mode, a memory controller must supply a plurality of these commands to the memory device based on a standardized latency. In particular, in accordance with the internal operation of the memory device, a column side operation must be started subsequent to a prescribed latency from the start of a row side operation, which tends to increase the resulting burden of control placed on the memory controller.
Conversely, to lessen the control burden of the above-described memory controller, a SyncLink DRAM has been newly proposed. The complete details thereof have yet to be clarified, but the basic specifications are such that a memory controller groups a command signal, a row address signal, a column address signal, awrite signal and a bank address signal, which is a kind of row address, into a packet and supplies this packet to a memory device in synch with an external clock. Column control for latency management need not be performed as with the above-described SDRAM. Consequently, the supply of the above-described packetized signal to 8 common input pins by time sharing it 4 times is being studied.
The above-described SyncLink DRAM can lessen the load on the memory controller, but on the memory device side, an internal operation must be controlled at a prescribed latency for a command, and a row address and a column address, which are provided at the same time. For example, for a read or write operation, whereby a command, and a row address and a column address are supplied simultaneously, subsequent to the supply of a command, latency must be controlled until the start of the column side operation subsequent to the end of the row side operation. Further, as with the burst mode in an SDRAM, it is also necessary to support a Read command and Write command, which are capable of consecutively accessing data of different column addresses at the same row address. In the case of this type of command, the latency from the supply of a command until the start of a column operation is short, unlike that of the above-described read/write operation. Thus, latency must be capable of changing in accordance with the supplied command.
Furthermore, there are also cases wherein latency is ependent on the capabilities (operating speed) of the memory device and the frequency of the clock by which it is driven. That is, even a mode register, by which the initial value of a memory device is set, must be able to change latency, which corresponds to various operation commands. Further, even in operations other than the column internal circuitry operations described above, latency control must be performed internally from the timing at which the command is supplied until a prescribed internal operation.
Therefore, a scheduler, which manages the schedule of an internal operation relative to the above-described request packet input is required inside a memory device. However, at present, a proposal for the above-described scheduler has yet to be made. And for large capacity, highspeed memory devices, suppressing current consumption is unavoidable. When providing such a scheduler, the suppression of current consumption must be taken into consideration.
Accordingly, an object of the present invention is to provide a clock-synchronized memory device like a SyncLink DRAM that solves for the above-described problems, and a memory device that comprises an appropriate scheduler.
Furthermore, another object of the present invention is to provide a memory device, which comprises a scheduler, which is small in size and suppresses current consumption.
Furthermore, another object of the present invention is to provide a scheduler, which is capable of being used in a SyncLink DRAM.